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application note vacuum fluorescent display module general description character display module futaba vacuum fluorescent display module M204SD02AJ, with futaba vfd 204-sd-02gn display, produces 20 digits4rows with 58 dot matrix. consisting of a vfd, one chip co ntroller, dc-dc/ac converter, the module can be operated by a parallel interface or a synchronous serial interface, and only 5 voltage power source is required to operate the module. an-e-2266a M204SD02AJ
an - e - 2266 a [important safety notice] important safety notice please read this note carefully before using the product. warning the module should be disconnected from the power supply before handling. the power supply should be switched off before connecting or disconnecting the power or interface cables. the module contains electronic components that generate high voltages which may cause an electrical shock when touched. do not touch the electronic components of the module with any metal objects. the vfd used on the mo dule is made of glass and should be handled with care. when handling the vfd, it is recommended that cotton gloves be used. the module is equipped with a circuit protection fuse. under no circumstances should the module be modified or repaired. an y u nauthorized modifications or repairs will invalidate the product warranty. the module should be abolished as the factory waste. !
an - e - 2266 a [contents] contents page 1. features 1 2. specifications 2 - 1. general specifications 1 2 - 2. environmental specifications 1 2 - 3. absolute maximum specifications 2 2 - 4. dc electrical specifications 2 2 - 5. ac electrical specifications 2 2 - 5 - 1. motorola m68 - type parallel interface timing 2 2 - 5 - 2. intel i80 - type parallel interface timing 4 2 - 5 - 3. synchronous serial interface timing 5 2 - 5 - 4. reset timing 7 3. mode of operation 3 - 1. parallel interface mod es 7 3 - 1 - 1. motorola m68 - type mode 7 3 - 1 - 2. intel i80 - type mode 8 3 - 2. synchronous serial interface mode 8 3 - 3. reset mode 9 4. functional description 4 - 1. address counter (ac) 10 4 - 2. display data ram (ddram) 10 4 - 3. character generator ram (cgram) 11 4 - 4. instructions 11 4 - 4 - 1. clear display 12 4 - 4 - 2. c ursor home 12 4 - 4 - 3. entry mode set 12 4 - 4 - 4. display on/off control 13 4 - 4 - 5. cursor/display shift 13 4 - 4 - 6. function set 14 4 - 4 - 7. cgram address set 14 4 - 4 - 8. ddram address set 14 4 - 4 - 9. address counter r ead 14 4 - 4 - 10. ddram or cgram write 15 4 - 4 - 11. ddram or cgram read 15 4 - 5. reset conditions 15 5. connector interface 16 6. jumper setting 16 7. circuit block diagram 16 figure - 1 mechanical drawing 17 figure - 2 character font table 18 8. warranty 19 9. operati ng recommendation 19
an - e - 2266 a [ 1 /19] 1. feature this vacuum fluorescent display (vfd) module consists of a 20 character by 4 line 5 8 dot matrix display, dc - dc/ac converter, and controller/driver circuitry. the module can be configured for a motorola m68 - type parallel interface, an intel i80 - type parallel interface, or a synchronous serial interface. a character generator rom with 240 5 8 characters is provided along with ram for the user to program an additional 8 characters. the luminance level of the vfd can be varied by setting two bits in the function set instruction. two hundred and forty character fonts consisting of a alphabets, numerals and other symbols can be displayed. this module has a dual - port ram that allows data and instructions to be sent to the module continuously. thus, the busy flag is always 0 and the host never has to read the busy flag bit to determine if the module is busy. due to this feature, the execution times for each instruction are not specified. 2. specifications 2 - 1. general specifications table - 1 item value number of characters 20 characters 4 lines character configuration 5 8 dot matrix character height 4.84 mm character width 2.35 mm character pitch 3.75 mm line pitch 8.71mm dot size 0.39 0.517mm dot pitch 0.49 0.618m peak wavelength of illum ination green ( l p=505nm) x=0.235, y=0.405 luminance minimum 350 cd/m 2 typical 500 cd/m 2 2 - 2. environmental specifications table - 2 item symbol min. max. unit comment operating temperature t opr - 40 +85 c storage temperature t stg - 55 +85 c o perating humidity h opr 20 85 %rh without condensation storage humidity h stg 20 90 %rh without condensation vibration - - 4 g total amplitude: 1.5mm freq: 10 - 55 hz sine wave sweep time: 1 min./cycle duration: 2hrs./axis (x,y,z) shock - - 40 g duration: 1 1ms wave form: half sine wave 3 times/axis (x,y,z, - x, - y, - z)
an - e - 2266 a [ 2 /19] 2 - 3. absolute maximum specifications table - 3 item symbol min. max. unit supply voltage v cc - 0.3 6.5 v input signal voltage v in - 0.3 v cc+0.3 v 2 - 4. dc electrical specifications ta ble - 4 item symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v supply current i cc - 300 400 ma power consumption - - 1.5 2.2 w high - level input voltage(see note) v ih 0.7 v cc - v cc v low - level input voltage v il 0 - 0.2 v cc v high - level ou tput voltage ( i oh = - 0.1ma) v oh v cc - 0.5 - - v low - level output voltage ( i ol = 0.1ma) v ol - - 0.5 v input current (see note) i i - 500 - 1.0 m a note: a 10k ohm pull - up resistor is provided on each input line. 2 - 5. ac electrical specifications 2 - 5 - 1. mo torola m68 - type parallel interface timing (see fig. 1 and 2) table - 5 item symbol min. max. unit rs, r/w setup time t as 20 - ns rs, r/w hold time t ah 10 - ns input signal rise time t r - 15 ns input signal fall time t f - 15 ns enable pulse width hi gh pw eh 230 - ns enable pulse width low pw el 230 - ns write data setup time t ds 80 - ns write data hold time t dh 10 - ns enable cycle time t cycle 500 - ns read data delay time t dd - 160 ns read data hold time t dhr 5 - ns note: all timing is specifie d using 20% and 80% of v cc as the reference points.
an - e - 2266 a [ 3 /19] fig. 1. motorola m68 - type parallel interface write cycle timing fig. 2. motorola m68 - type parallel interface read cycle timing t dh t ah t as t f t r t ds rs r/w e db0 - db7 t cycle pw eh pw el rs r/w e db0 - db7 t dhr t ah t as t f t r t dd t cycle pw eh pw el
an - e - 2266 a [ 4 /19] 2 - 5 - 2. intel i80 - type parallel interface timing (see fig. 3 and 4) table - 6 item symbol min. max. un it rs setup time t rss 10 - ns rs hold time t rsh 10 - ns input signal fall time t f - 15 ns input signal rise time t r - 15 ns wr/ pulse width low t wrl 30 - ns wr/ pulse width high t wrh 100 - ns write data setup time t dsi 30 - ns write data hold time t dhi 10 - ns wr/ cycle time t cycwr 166 - ns rd/cycle time t cycrd 166 - ns rd/ pulse width low t rdl 70 - ns rd/ pulse width high t rdh 70 - ns read data delay time t ddi - 70 ns read data hold time t dhri 5 50 ns note: all timing is specified using 20% and 80% of v cc as the reference points. fig. 3. intel i80 - type parallel interface write cycle timing db0 - db7 t f t dhi t r t rsh t rss t dsi t cycwr wr/ rs t wrl t wrh
an - e - 2266 a [ 5 /19] fig. 4. intel i80 - type parallel interface read cycle timing 2 - 5 - 3. synchronous serial interface timing (see fig. 5, 6, 10, and 11) table - 7 item symbol min. max. unit stb setup time t stbs 100 - ns stb hold time t stbh 500 - ns input signal fall time t f - 15 ns input signal rise time t r - 15 ns stb pulse width high t wstb 500 - ns sck pulse width high t sckh 200 - ns sck pulse width low t sckl 200 - ns si data setup time t dss 100 - ns si data hold tim e t dhs 100 - ns sck cycle time t cycsck 500 - ns sck wait time between bytes t wait 1 - us so data delay time t dds - 150 ns so data hold time t dhrs 5 - ns note: all timing is specified using 20% and 80% of v cc as the reference points. db0 - db7 t f t dhri t r t rsh t rss t ddi t cycrd rd/ rs t rdl t rdh
an - e - 2266 a [ 6 /19] fig. 5. synchronous serial interface write cycle timing fig. 6. synchronous serial interface read cycle timing t dhs t sckl t dss t r t f t wstb stb t stbh t cycsck t stbs t sckh sck si/ so t dhs t sckl t dds t r t f t wstb stb t stbh t cycsck t stbs t sckh sck si/so
an - e - 2266 a [ 7 /19] 2 - 5 - 4. reset timing (see fig. 7) table - 8 item symbol min. max. unit delay time for internal reset at power - up t rstd 100 - ms v cc off time t off 1 - ms fig. 7. p ower - up internal reset timing 3. mode of operation the following modes of operation are selectable via jumpers (see section 6. jumper settings). 3 - 1. parallel interface modes in the parallel interface mode, 8 - bit instructions and data are sent between th e host and the module using either 4 - bit nibbles or 8 - bit bytes. nibbles are transmitted high nibble first on db4 - db7 (db0 - db3 are ignored) whereas bytes are transmitted on db0 - db7. the register select (rs) control signal is used to identify db0 - db7 as an instruction (low) or data (high). 3 - 1 - 1. motorola m68 - type mode this mode uses the read/write (r/w) and enable (e) control signals to transfer information. instructions/data are written to the module on the falling edge of e when r/w is low and are read f rom the module after the rising edge of e when r/w is high. fig. 8. typical 4 - bit interface sequence using m68 - type mode bf= ?0? db7 db6 db5 db4 rs r/w e ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 ib6 ib5 ib4 ib3 ib2 ib1 ib0 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 write instruction write instruction read instruction write data 4.5v 0.2v vcc t off t rstd stb
an - e - 2266 a [ 8 /19] 3 - 1 - 2. intel i80 - type mode this mode uses the read (rd/) and write (wr/) control signals to transfer information. instructions/data are written to the module on the rising edge of wr/ and are read from the module after the falling edge of rd/. fig. 9. typical 8 - bit parallel interface sequence using i80 - type mode 3 - 2. synchronous serial interface mode in the synchronous serial interface mode, instructions and data are sent between the host and the module using 8 - bit bytes. two bytes are required per read/write cycle and are transmitted msb first. th e start byte contains 5 high bits, the read/write (r/w) control bit, the register select (rs) control bit, and a low bit. the following byte contains the instruction/data bits. the r/w bit determines whether the cycle is a read (high) or a write (low) cycl e. the rs bit is used to identify the second byte as an instruction (low) or data (high). this mode uses the strobe (stb) control signal, serial clock (sck) input, and serial i/o (si/so) line to transfer information. in a write cycle, bits are clocked int o the module on the rising edge of sck. in a read cycle, bits in the start byte are clocked into the module on the rising edge of sck. after the minimum wait time, each bit in the instruction/data byte can be read from the module after each falling edge of sck. each read/write cycle begins on the falling edge of stb and ends on the rising edge. to be a valid read/write cycle, the stb must go high at the end of the cycle. db7 db6 db0 bf=?0? ib6 ib0 ib7 ib6 ib0 ib7 ib6 ib0 rs wr/ rd/ db7 db6 db0 write instruction write instruction read instruction write data
an - e - 2266 a [ 9 /19] fig. 10. typical synchronous serial interface write cycle fig. 11. typical synchronous serial interface read cycle 3 - 3. reset mode the module is reset automatically at power - up by an internal r - c circuit. rs r/w b0 b1 b2 b3 b4 b5 b6 b7 ?0? ?1? ?1? ?1? ?1? stb sck si/so 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ?1? start byte instruction / data 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 stb sck si/so rs r/w ?0? ?1? ?1? ?1? ?1? ?1? b0 b1 b2 b3 b4 b5 b6 b7 start byte instruction / data
an - e - 2266 a [ 10 /19] 4. func tional description 4 - 1. address counter (ac) the ac stores the address of the data being written to and read from ddram or cgram. the ac increments by 1 (overflows from 27h to 40h and from 67h to 00h) or decrements by 1 (underflows from 40h to 27h and from 00h to 67h) after each ddram access. the ac increments by 1 (overflows from 3fh to 00h) or decrements by 1 (underflows from 00h to 3fh) after each cgram access. when addressing ddram, the value in the ac also represents the cursor position. 4 - 2. display data ram (ddram) the ddram stores the character code of each character being displayed on the vfd. valid ddram addresses are 00h to 27h and 40h to 67h. ddram not being used for display characters can be used as general purpose ram. the tables below show t he relationship between the ddram address and the character position on the vfd before and after a display shift (with the number of display lines set to 2). relationship before a display shift (non - shifted): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 2 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 3 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 4 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 relationship after a display shift to the left: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 2 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 3 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 00 4 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 40 relationship after a display shift to the right: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 27 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 2 67 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 3 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 4 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66
an - e - 2266 a [ 11 /19] 4 - 3. character generator ram (cgram) the cgram stor es the pixel information (1 = pixel on, 0 = pixel off) for the eight user - definable 5 8 characters. valid cgram addresses are 00h to 3fh. cgram not being used to define characters can be used as general purpose ram. character codes 00h to 07h (or 08h to 0f h) are assigned to the user - definable characters (see section 5.0 character font tables). the table below shows the relationship between the character codes, cgram addresses, and cgram data for each user - definable character. character code cgram address c gram data d7 d6 d5 d4 d3 d2 d1 d0 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 cgram (1) 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 1 0 cgram (2) 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1 cgram (8) 4 - 4. instructions table - 9 instruction rs r/w db7 db6 db5 db4 d b3 db2 db1 db0 clear display 0 0 0 0 0 0 0 0 0 1 cursor home 0 0 0 0 0 0 0 0 1 entry mode set 0 0 0 0 0 0 0 1 i/d s display on/off control 0 0 0 0 0 0 1 d c b cursor/display shift 0 0 0 0 0 1 s/c r/l function set 0 0 0 0 1 dl n br1 br0 cgram address set 0 0 0 1 cgram address ddram address set 0 0 1 ddram address address counter read 0 1 bf=0 ac contents ddram or cgram write 1 0 write data ddram or cgram read 1 1 read data =don?t care
an - e - 2266 a [ 12 /19] 4 - 4 - 1. clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 1 this instruction clears the display (without affecting the contents of cgram) by performing the following. 1) fills all ddram locations with character code 20h (character code for a space). 2) sets the ac to ddram address 00 h (i.e. sets cursor position to 00h). 3) returns the display to the non - shifted position. 4) sets the i/d bit to 1. 4 - 4 - 2. cursor home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 =don?t care this instruction returns the cursor to the h ome position (without affecting the contents of ddram or cgram) by performing the following. 1) sets the ac to ddram address 00h (i.e. sets cursor position to 00h). 2) returns the display to the non - shifted position. 4 - 4 - 3. entry mode set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d s this instruction selects whether the ac (cursor position) increments or decrements after each ddram or cgram access and determines the direction the information on the display shifts after each ddram write. the instruction also enables or disables display shifts after each ddram write (information on the display does not shift after a ddram read or cgram access). ddram, cgram, and ac contents are not affected by this instruction. i/d = 0 : the ac decrements after each ddram or cgram access. if s=1, the information on the display shifts to the right by one character position after each ddram write. i/d = 1 : the ac increments after each ddram or cgram access. if s=1, the information on the display shifts to t he left by one character position after each ddram write. s = 0 : the display shift function is disabled. s = 1 : the display shift function is enabled.
an - e - 2266 a [ 13 /19] 4 - 4 - 4. display on/off control rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c b this instruction selects whether the display and cursor are on or off and selects whether or not the character at the current cursor position blinks. ddram, cgram, and ac contents are not affected by this instruction. d = 0 : the display is off (display blank) . d = 1 : the display is on (contents of ddram displayed). c = 0 : the cursor is off. c = 1 : the cursor is on (8 th row of pixels). b = 0 : the blinking character function is disabled. b = 1 : the blinking character function is enabled (a character with all pixels on will alternate with the character displayed at the current cursor position at about a 1hz rate with a 50% duty cycle). 4 - 4 - 5. cursor/display shift rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 s/c r/l =don?t care this instruct ion increments or decrements the ac (cursor position) and shifts the information on the display one character position to the left or right without accessing ddram or cgram. ddram and cgram contents are not affected by this instruction. if the ac was addre ssing cgram prior to this instruction, the ac will be addressing ddram after this instruction. however, if the ac was addressing ddram prior to this instruction, the ac will still be addressing ddram after this instruction. table - 10 s/c r/l ac content s (cursor position) information on the display 0 0 decrements by one no change 0 1 increments by one no change 1 0 decrements by one shifts on character position to the left 1 1 increments by one shifts on character position to the right
an - e - 2266 a [ 14 /19] 4 - 4 - 6. f unction set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n br1 br0 =don?t care this instruction sets the width of the data bus for the parallel interface modes, the number of display lines, and the luminance level (brightness) of the vfd. dd ram, cgram, and ac contents are not affected by this instruction. dl = 0 : sets the data bus width for the parallel interface modes to 4 - bit (db7 - db4). dl = 1 : sets the data bus width for the parallel interface modes to 8 - bit (db7 - db0). n = 0 : sets the number of display lines to 1 (this setting is not recommended). n = 1 : sets the number of display lines to 2 br1, br0 = 0,0: sets the luminance level to 100%. 0,1: sets the luminance level to 75%. 1,0: sets the luminance level to 50%. 1,1: s ets the luminance level to 25%. 4 - 4 - 7. cgram address set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 cg ram address this instruction places the 6 - bit cgram address specified by db5 - db0 into the ac (cursor position). subsequent data writes (reads) w ill be to (from) cgram. ddram and cgram contents are not affected by this instruction. 4 - 4 - 8. ddram address set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 dd ram address this instruction places the 7 - bit ddram address specified by db6 - db0 into the a c (cursor position). subsequent data writes (reads) will be to (from) ddram. ddram and cgram contents are not affected by this instruction. 4 - 4 - 9. address counter read rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 bf=0 ac contents this instruction reads the current 7 - bit address from the ac on db6 - db0 and the busy flag (bf) bit (always 0) on db7. ddram, cgram, and ac contents are not affected by this instruction. because the bf is always 0, the host never has to read the bf bit to determine if the module is busy before sending data or instructions. therefore, data and instructions can be sent to the module continuously according to the e, wr/, and sck cycle times specified in section 2.5 ac timing specifications. due to this feature, the execution times fo r each instruction are not specified.
an - e - 2266 a [ 15 /19] 4 - 4 - 10. ddram or cgram write rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data this instruction writes the 8 - bit data byte on db7 - db0 into the ddram or cgram location addressed by the ac. the most recent ddram or cgram address set instruction determines whether the write is to ddram or cgram. this instruction also increments or decrements the ac and shifts the display according to the i/d and s bits set by the entry mode set instruction. 4 - 4 - 11. ddram or cgra m read rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data this instruction reads the 8 - bit data byte from the ddram or cgram location addressed by the ac on db7 - db0. the most recent ddram or cgram address set instruction determines whether the read i s from ddram or cgram. this instruction also increments or decrements the ac and shifts the display according to the i/d and s bits set by the entry mode set instruction. before sending this instruction, a ddram or cgram address set instruction should be e xecuted to set the ac to the desired ddram or cgram address to be read. 4 - 5. reset conditions after a power - up reset, the module initializes to the following conditions: 1)all ddram locations are set to 20h (character code for a space). 2)the ac is set to ddram address 00h (i.e. sets cursor position to 00h). 3)the relationship between ddram addresses and character positions on the vfd is set to the non - shifted position. 4)entry mode set instruction bits: i/d = 1: the ac increments after each ddram or cgr am access. if s=1, the information on the display shifts to the left by one character position after each ddram write. s = 0: the display shift function is disabled. 5)display on/off control instruction bits: d = 0: the display is off (display blank). c = 0: the cursor is off. b = 0: the blinking character function is disabled. 6)function set instruction bits: dl = 1: sets the data bus width for the parallel interface modes to 8 - bit (db7 - db0). n = 1: number of display lines set to 2. br1,br0=0,0: sets the l uminance level to 100%.
an - e - 2266 a [ 16 /19] 5. connector interface table - 11 pin no. serial parallel (intel) parallel (motorola) pin no. serial parallel (intel) parallel (motorola) 1 gnd gnd gnd 2 vcc vcc vcc 3 si/so nc nc 4 stb rs rs 5 nc wr/ r/w 6 sck rd/ e 7 nc db0 db0 8 nc db1 db1 9 nc db2 db2 10 nc db3 db3 11 nc db4 db4 12 nc db5 db5 13 nc db6 db6 14 nc db7 db7 nc = no connection 6. jumper setting table - 12 mode j3 j4 j5 j6 j7 parallel (motorola) open shorted open shorted open parallel (intel) o pen shorted open open shorted serial shorted open shorted shorted open note : jp3 - jp7 must be set as shown above for either one of the parallel modes or for the serial mode. when the module is shipped , the parallel (motorola) mode is set. 7. circuit block diagram vacuum fluorescent display 204 - sd - 02gn grid driver dot matrix vfd control ler & driver dc - dc/ac converter nc_rst/_si/so rs_stb r/w_wr/ e_rd/_sck db0 - db7 vcc gnd
an-e-2266a [17/19] M204SD02AJ mechanical drawing figure-1
an-e-2266a [18/19] M204SD02AJ character font tables (english/european font) figure-2 d7 d6 d5 d4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef d3 d2 d1 d0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 sp : space sp
an - e - 2266 a [ 19 /19] 8. warranty this display module is guaranteed for 1 year after a sh ipment from futaba. 9. operating recommendation 9 - 1. since vfds are made of glass material. avoid applying excessive shock or vibration beyond the specification for the module. careful handing is essential. 9 - 2. applying lower voltage than the specified may cause non activation for selected pixels. conversely, higher voltage may cause may non - selected pixel to be activated. if such a phenomenon is observed, check the voltage level of the power supply. 9 - 3. avoid plugging or unplugging the interface conn ection with the power on. 9 - 4. if the start up time of the supply voltage is slow, the controller may not be reset. the supply voltage must be risen up to the specified voltage level within 30msec. 9 - 5. avoid using the module where excessive noise interf erence is expected. noise affects the interface signal and causes improper operation. keep the length of the interface cable less than 50cm (when the longer cable is required, please contact futaba engineering.). 9 - 6. when power supply is turned off, the capacitor does not discharge immediately. the high voltage applied to the vfd must not contact the controller ic. (the shorting of the mounted components within 30 seconds after power off may cause damage.) 9 - 7. the fuse is mounted on the module as circu it protection. if the fuse blown, the problem shall be solved first and change the fuse. 9 - 8. when fixed pattern is displayed for long time, you may see uneven luminance. it is recommended to change the display patterns sometimes in order to keep best dis play quality. remarks this specification is subject to change without prior in order improve the design and quality. your consultation with futaba sales office is recommended for the use of this module.

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